Today's integrated circuits include a vast number of devices. Smaller devices and shrinking ground rules are the key to enhance performance and to reduce cost. As FET (Field-Effect-Transistor) devices are being scaled down, the technology becomes more complex, and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement from one generation of devices to the next. The mainstay material of microelectronics is silicon (Si), or more broadly, Si based materials. One such Si based material of importance for microelectronics is the silicon-germanium (SiGe) alloy. The devices in the embodiments of the present disclosure are typically part of the art of single crystal Si based material device technology.
There is great difficulty in maintaining performance improvements in devices of deeply submicron generations. Therefore, methods for improving performance without scaling down dimensions have become of interest. There is a promising avenue toward higher gate capacitance without having to make the gate dielectric actually thinner. This approach involves the use of so called high-k materials. The dielectric constant of such materials is higher than that of SiO2, which is about 3.9. A high-k material may physically be thicker than an oxide, and still have a lower equivalent oxide thickness (EOT) value. The EOT, a concept known in the art, refers to the thickness of such an SiO2 layer which has the same capacitance per unit area as the insulator layer in question. In today state of the art FET devices, one is aiming at an EOT of below 2 nm, and preferably below 1 nm.
Device performance is also enhanced by the use of metal gates. The depletion region in the poly-Si next to the gate insulator can become an obstacle in increasing gate-to-channel capacitance. The solution is to use a metal gate. Metal gates also assure good conductivity along the width direction of the devices, reducing possible RC delays in the gate.
High performance small FET devices are in need of precise threshold voltage control. As operating voltage decreases, to 2V and lower, threshold voltages also have to decrease, and threshold variation becomes less tolerable. Every new element, such as a different gate dielectric, or a different gate material, influences the threshold voltage. Techniques exist to tune device thresholds through the modification of the gate workfunction. Typically such techniques are complicated, involving many masking steps. There is need for simpler fabrication methods for threshold tuned CMOS structures and circuits.